International Journal of LNCT

ISSN (Online):2456-9895

 

 

Volume-2 Issue-5 April-2018

[1]  Analysis of (SRAM) static random access memory power consumption



Vineet Singh and Sourabh Pandey


SRAM is a very critical component in several of the digital systems and electronic devices, from high-performance processors to mobile-phone chips. Power and system performance are the essential parameters for all applications. SRAM is small semiconductor memory cell. It is used one bit data for information storage in the form of electrical signal. It provides very fast speed operation and power consumption are very less as compared to other memory cells [1]. Portable electronic devices which are battery operated in which power consumption is major concern. The total power consumption in commercial processors and application specific integrated circuits increases with decreasing technology nodes. Total Power saving techniques in system has become a first class design point for current and future VLSI systems. Currently this technique is applied to study the power savings in application specific integrated circuit SRAM memories and can also be applied for commercial processors. By adding simple, low-overhead parity, an error-correction capability is added to the memory architecture for robust soft-error protection. Low power consumption in memory plays an important part in VLSI. But the memory consumes more power. The sub-threshold leakage power is the main reason for high power consumption.

[2]  Review of spam classification using different machine learning algorithms



Aditya Shrivastava and Rachana Dubey


Email is necessary and essential for communication in today's life. Today internet users are increases, and email is necessary for communication over the internet. Spam mail is a major and big problem of researchers to analyze and reduce it. Spam emails are received in bulk amount and it contains trojans, viruses, malware and causes phishing attacks. Problems are arise when number of unwanted mails are come from unknown sites and how to classify the user that email are received which is spam email or ham. This paper used to classify that incoming emails are spam mail or ham by the use of different classification techniques to identify spam mail and remove it. This paper benchmark dataset is used. The dataset contains 58 attributes and 4601 instances used to build a model. These papers play a very important role to remove viruses, trojans, malware and websites including phishing attacks and fraudulent attempts in emails. Different Classification algorithms are used like Naive Baye's, Random Forest and Random Tree are applied on spam dataset.

[3]  Review of reversible encoder and decoder using reversible gate



Shailendra Band and Monika Kapoor


In today's world reversible encoder and decoder is one of the very important parts of any system having many applications in computers, mobile, calculators etc. Reversible logic is useful in mechanical applications of nanotechnology, given that the friction generated by contacting corpuscles within a confined volume can be significantly reduced by eliminating sliding contact using mechanical reversible logic. We have implemented reversible arithmetic logic unit based on reversible encoder and decoder. The problem of minimizing the number of garbage outputs is an important issue in reversible logic design. Reversible encoder and decoder are consisting of different gate.

[4]  Review Paper on FIR filter based on vedic multiplier and kogge stone adder



Piyush Gour and Santosh Jha


Increase is a critical capacity in number-crunching activities. A CPU (focal handling unit) dedicates a lot of preparing time in performing number juggling tasks. Increase requires generously more hard-product assets and handling time than expansion and sub-footing. Computerized flag processors (DSPs) are the innovation that is ubiquitous in building Discipline. Quick duplication is essential in DSPs for advanced channel, convolution, Fourier changes and so on. In this proposed research work an attempt will make for making a novel FIR filter using Vedic multiplier modified Kogge stone adder. The implementation FIR filter based on Vedic multiplier will have not only fast response but also having less number of component, area and path delay.

[5]  Retailer transaction details



Neha Nema, Nitish Kumar, Pawan Chaurasiya and Manish Shrivashtava


Retailer Transaction Details is a Software solution which allows a particular retailer shop or whole seller to arrange, conduct and manage transaction via an online environment. This can be done through the Internet, Intranet and Local Area Network. Some of the problem faced by manual transaction systems are complicated in managing the buying and selling, filing poses a problem, filtering of records is not easy. The possibility of loss of records is higher and searching process of record is difficult. Maintenance of the record is also very difficult and takes a lot of time and efforts. Retailer Transaction Details was necessary to separate interaction with customers and maintaining the records. A web-based Retailer Transaction Details was developed with Java Web technologies. The RTD provided the features, including GST management, gross profit of seller and total revenue. In RTD web application, both server side and client side application helps to maintain data. With the development of the Internet and network database, online transaction has become an important method of maintaining business, marketing, and awareness. So how to achieve the goals of informational and paperless transaction better, and make the record maintaining more efficient, onvenient and justice become an important topic in the modern business field. Developing a stable online Retailer Transaction Details can effectively solve this problem. Online trasaction system is a web-based project. It ssesses retailer or whole-seller by taking regular use of this application. This application is customizable. Admin can set table for requirement. This project will be useful for any retailer shop, whole-seller or any mall like Big-bazar, India Mart etc.

[6]  Study of student campus eligibility portal



Saleena Qureshi, Shubhi Verma, Ragini Saxena and Manish Shrivastava


Every year hundreds of students from various colleges take campus recruitment test. This test is organized by a huge number of companies who are in search for dexterous and talented students to recruit for their company. This process of handpicking each and every student suitable for a particular job profile can be a tedious process for both the students and the companies. Every company has a predefined eligibility criterion, students who are able to fulfill this eligibility criteria are only allowed to sit for the further recruitment process. This project is directed to resolve the problem of superfluous eligibility criteria, which makes this process decipherable and highly accessible. Since each company has its own eligibility criteria there are very high chances of them being redundant hence confusing the students. One striking solution for this redundancy is to compile the eligibility criteria of various organizations on a single portal that can be accessible by the students to check the number of companies in which they are eligible. This project is made keeping in mind that it provides solution from end to end. Since the recruitment drive is a tedious drive we reduce the stress level by a notch, by just one click the students will know the companies in which they are eligible and can easily start preparing for the further levels. This will give the preparation of the students a kick-start. The project is helpful for the companies as well because this portal will provide them with a clear view of the number of students who are eligible for the company and other personal details of the students, which it can use for further indications.

[7]  Survey of recent advancement in big data analytics for business operations and risk

management prospective




Shikha Jaiswal and Vineet Richarya


Big data analytics would definitely lead to valuable knowledge for many organizations. Business operations and risk management can be a beneficiary as there are many data collection channels in the related industrial systems (e.g., wireless sensor networks, Internet-based systems, etc.). Big data research, however, is still in its infancy. Technological development and advances for industrial-based business systems, reliability and security of industrial systems, and their operational risk management are examined. This paper aims to focus performing different analysis of business operations and risk management.

[8]  Current fog computing challenges for location privacy preservation in cloud networks



Diksha Singh Gour and Vineet Richhariya


In the current decade the mobility of communication devices faces a problem of location privacy preservation. Fog computing extends the edge network of cloud computing. Fog computing faces new security and privacy challenges besides those inherited from cloud computing. The edge network of cloud computing has multiple servers in form of mobility. The mobility of edge server is an open stack communication. The open stack communication invites security threats and malware software for the denial of services delivered by fog computing. This paper presents the review of location privacy preservation techniques in fog computing based on different location scenario and different cryptography techniques for location preservation of edge servers and edge device.

[9]  Survey of efficient remote data possession checking protocol in cloud storage



Rashmi Dwivedi, Sunil Phulre, and Sadhana K Mishra


Cloud storage offers the users with top quality and on-demand information storage services and frees them from the burden of maintenance. Cloud computing has been pictured because the on-demand self-service, present network access, location independent resource pooling, speedy resource elasticity, usage-based evaluation and transference of risk. Today, technical analyses works specialize in Remote information possession checking protocols allow examining that an overseas server will access an uncorrupted file with the assistance of third party verifiers. Remote information integrity checking is very important in cloud storage. It will build the purchasers verify whether their information is kept because it is while not downloading the complete information. In some application situations, the purchasers got to store their information on multi-cloud servers. At a similar time, the integrity checking protocol should be efficient so as to save the verifier's price.

[10]  Dynamic load balance using enhanced AOMDV routing in MANET



Pooja Raikwar,Hitesh Gupta and Sadhna K. Mishra


The link in dynamic network is failure due to movement of nodes and these nodes speed is also not similar. The nodes in MANET having different mobility speed and the reason is data not received at destination, if link is congested. The message is sends by sender and the number of data packets of messages are blocked in link is occurring the possibility of congestion. Multipath routing is the one of the solution to resolve the congestion by splitting the extra load. Thus multipath AOMDV protocol is able to reducing the congestion by dividing the traffic in several paths. In this research work we proposed the congestion control multipath queue estimation routing to divide the load in network efficiently. IN AOMDV the link failures in the primary path, through which data is sending actually taking place, cause the source to choose an alternate path instead of initiating another route establishment. The proposed approach can result is reduced delay since packets stored in queue buffered is also forward to other nodes when an alternate path is available. The proposed approach is provides the technique to estimate the queue size at the time of sending data packets to destination node and if the destination node. The TALB-AOMDV protocol is also estimate the buffer size but it also measure the buffer size with respect to previous transmission. The proposed scheme is not compare the queue size with previous data but enhance the queue size if the packets incoming is also fast. After all the congestion possibility is removes by handling the packets and also the data packets forwarded by intermediate nodes the queue size is again reach to normal level. The performance of proposed scheme is evaluated through different performance metrics and simulated in NS-R simulator.

[11]  A review on architecture of FFT based montgomery multiplication



Vijeta Raichur, and Laxminarayan Gahalod


As the scale of integration keeps growing; more and more sophisticated signal processing systems are being implemented on a VLSI chip. These signal processing applications not only demand great computation capacity but also consume considerable amount of energy. While performance and Area remain to be the two major design tolls, power consumption has become a critical concern in today's VLSI system design. Unceasing advancement in microelectronics design technology makes improved use of energy, encrypt data successfully, communicate information much more steadfastly, etc. Particularly, many of these technologies address low-power consumption to meet the requirements of various portable applications. Multiplication is a fundamental operation in most signal processing algorithms. Multipliers have large area, long latency and consume considerable power. Therefore low-power high speed and small in size multiplier design has been an important part in modern VLSI system design. Montgomery modular multiplication (MMM) is an efficient method to compute modular multiplication. In this work an extensive survey of literature review based on Montgomery Multiplication has given.

[12]  Clock gating techniques for the design of arithmetic and logic unit-a survey



Shikha, Prashant Chaturvedi and Monika Kapoor


This is often an era of devices which may be control in hands like cell phones, and private digital assistants. Since processors are often embedded in these devices this has became attainable. The 2 parameters that are important within the design of those systems are there in operation speeds and standby time. This paper presents a comparative study on different clock gating technique to cut back dynamic power consumption.

[13]  An extensive survey on weighted partitioning for multiple-constant convolution fast multiplierless circuit



Deepak Tiwari and Prashant Purohit


The graph partitioning issue is a deliberation of this utilization case there are additionally lots of other applications of the issue. Simulations using the finite element method, forms during VLSI configuration, route planning and logical processing all prompt or advantage from solving a graph partitioning problem. Gaussian convolutions are maybe the frequently utilized a graph partitioning problem in low-level PC vision undertakings. The discrete convolution kernel is when all is said in done not equivalent to the examined rendition of the consistent convolution bit. It turns out to be the inspected adaptation of the convolution of the consistent convolution kernel and the continuous interpolation kernel. Multiplication and Fast Fourier Transform are essential devices utilized as a part of the Digital Signal Processing applications. Every one of them is register escalated segment of broadband beam forming applications, for example, those by and large utilized as a part of software characterized radio and sensor systems. These are often utilized bit tasks in signal and image processing including versatile frameworks. This work reported a broad study on different constant convolution fastmultiplierless Circuit in view of weighted partitioning algorithm.

[14]  Improving the performance of solar stills using pre heating the copper tube



Sourabh mishra, Vipin sharma, Jitendra Raghuwanshi


All over the world there is a scarcity of water and it is difficult to access potable water. Due to this most of the people are affected by diseases that are caused due to drinking of polluted water. There are technologies through which we can purify waste water but the only problem is these technologies uses electrical energy. Since solar energy is abundant in nature therefore we can use solar as a energy source in solar stills for water distillation. Solar stills can be used in village areas where there is no electricity. It is simple and also economic in construction. This article is detailed study in solar distillation Conventional means of providing potable water, especially from fossil fuel, is becoming increasingly expensive and might be unreasonable by the poorest countries of the world where water and sanitation is a major challenge. There is a need to find viable alternative sources of energy. Various renewable energy sources were explored and the solar energy is adjudged the best option. With abundance of solar energy in many of the poorest parts of the world where access to potable water is a challenge; it is reasoned that this is the best and most viableoption.

[15]  Review paper on hybrid LUT/MUX combinational architecture



Shaili Jain, Shashilata Rawat and Monika Kapoor


Hybrid combinational architectures are used for FPGA's which consists of different combinations of LUT's and hardened multiplexers are evaluated for achieving the goal of greater logic density and area minimization. Various Technology mapping optimizations which target the proposed architectures are also implemented within the circuit. All calculating for CLB's and routing area while retaining mapping extent. For divisible architectures, the proposed architecture of this paper, analyzes the logic size, area and power consumption using Xilinx 14.2.

[16]  Design of power and area optimized ALU for FPGA



Shikha Gupta, Prashant Chaturvedi and Monika Kapoor


In this work we have implemented an arithmetic and logic unit with clock gating and hardware sharing method. In our design we have used clock gating technique to implement arithmetic and logic unit. Using this method we have successfully reduced the dynamic power consumption by reducing switching activity inside the design. The dynamic power consumption is decreased by 21% for 8 operation design compared to other design available in literature and 12.2% for 15 operation design.. We have also used hardware sharing method for four instructions; this reduces the hardware usage of FPGA. The Resource usage is reduced by 29% for 8 operations design and by 2.2 & for 15 operation design.

[17]  Implementation aspects of Radix-N adder with analysis of Radix-4



Deepak Jain and M. Zahid Alam


Increasing of calculation in various operations arithmetic circuits needs to be increased capability. With various Improvements in the VLSI technology submicron dimension the various other algorithms and implementation concepts should be improved. Traditionally Radix-2 binary logic circuits used which have 0,1 two symbol to represents then Radix–4 quaternary logic which have 0,1 ,2,3 symbols representation has been used. Then we can further have increased the concept to the Radix- N logic implementation which can have N symbols to represent. Various advantages of power utilization and improved switching delays will be there.

[18]  Improvement in voltage and power of transmission system by Static

VAR compensator (SVC) and transformer tapping using MATLAB




Atul Prakash Singh and Vivek Rai


The Flexible AC (Facts) transmission system controllers, such as Static Var Compensator (SVC), uses the latest electronic switching equipment technology in the electrical transmission system to control voltage and power flows and improve stability short-term tension. Both Tap-changing transformers and stable VAR compensators can contribute to the stability of the supply system voltage. The combination of these two methods is the subject of this thesis. The effect of the presence of tap changing transformers is highlighted on the value required to stabilize the parameters of the constant variable compensator controller and to stabilize the load voltage on specific values. Relation between the off nominal tap ratios and the SVC controller gain and Relation of the transformer parameters with the droop slope and the SVC rating and difference between them. For all major power systems represented by two-node systems, the power / voltage curves are detected and their impact on the maximum power / significant voltage is investigated. Several studies have found that automatic tap transformers can be used to improve voltage stability for both static and transient voltage stabilizers. Some of them were interested in the study, the new model for the tap-changer transformer used in the second, the use of static VAR compensator stable, to improve the voltage stability due to opening or recovery lines short circuit in the presence of the induction motor etc. The main goal of this thesis is to make the effects of single-transformer is the first part of this thesis. In other study, only the effects of the static VAR compensator (SVC) are given with series capacitor. The effect of the bypass transformer, the reference voltage values and the evaluation of the advantage of the compensator are given in detail. The study system shows all major systems seen from the load node in question.

[19]  An comprehensive study weighted partitioning for multiple-constant convolution

circuit to design fast multipliers




Deepak Tiwari and Prashant Purohit


The graph partitioning issue are utilized as a part of performance radar systems. The circle channel is connected in a criticism circle. The circle channel is a FIR channel. FIR channels can be actualized with multiplier hinders using Multiple Constant Multiplication(MCM). MCM replaces consistent augmentations by adders and shifts. Movements can be hardwired in usage so the last cost of the plan can be estimated by the quantity of adders/subtractors. For longer sift where consistent increase turns through more cumbersome MCM makes such plans basic. There are a few algorithms to take care of the MCM issue. In this work method for quick convolution algorithms is to express convolution activities with the ideas and apparatuses of another numerical field. This encourages it to apply techniques from this field to the first issue is a foundation of transformation based fast convolution algorithms-like FFT-based fast convolution. It makes utilization of polynomial insertion to determine streamlined conditions for discrete convolutions, with less terms than the discrete convolution entirety. To wrap things up numbered hypothesis prompt many, regularly progressive, new methodologies. Huge numbers of these systems were considered in the zone of quick Fourier change algorithms and after that later connected to convolution techniques too. This work exhibits a broad review on numerous consistent convolution quick multiplierless Circuit in view of weighted partitiioning algorithm.

[20]  A review on residue module arithmetic's adder and sub-tractor



Pradeep Upadhyay and Ramanand Singh


Due to the increasing spread of digital computing, investigation of various number representation systems in the digital field seems necessary. In general, the number representation systems regarding their applications can be classified in two areas: general-purpose and specific-purpose. Binary Digit Residue Number System (BD-RNS) is one of the specific-purpose and optimized number system. In Residue Number System-based systems, how to select moduli set and evaluate its performance is an important issue. The objective of this study is to propose a systemic performance evaluation method for RNS based on the properties of moduli set. By abstracting the inherent properties of moduli sets, such as the complexity of arithmetic units, utilization ratio of dynamic range, parallelism and balance between residue channels, this method can provide advices on moduli set selection and carry out performance estimation before circuit's implementation.

[21]  Survey of low power and area efficient XOR/XNOR gate using CMOS logic design



Kirti Dhakad and Shraddha Shrivastava


The quick developments of compact electronic gadgets are expanded and they are planning with low power and rapid is basic. To plan a three info XOR and XNOR entryways utilizing the methodical cell outline philosophy can be accomplished by actualizing transmission door. By this kind of planning the low power and fast can accomplished. This engineering is utilized to keep up summation comes about for subsequent to finishing expansion process.

[22]  Steady state analysis of thermal fins having different cross sections



Yogesh Chouksey and Jitendra Raghuwanshi


Various researches are being done on the design of thermal fins so as to improve their effectiveness and efficiency while reducing their weight or manufacturing cost. This work is related to one such analysis. In this work steady state analysis using ANSYS is done on fins having different types of cross sections viz. rectangular, triangular and elliptical. The length, width and area of cross section of these fins are identical while maximum thickness varies to compensate for the area of cross section. The initial and all other conditions are same for the analysis of these fins and the only difference is in their shape. Finally tip temperature and heat flux at base is plotted, while effectiveness and efficiency was compared. The software used to create models was CATIA V5.

[23]  An extensive review onFFT based montgomery multiplication algorithm



Vijeta Raichur and Laxminarayan Gahalod


The role of network security in the field of networking, is immense. In the information era it is important to keep information secure about every aspect of our live. Hence to keep the information securely is known as cryptography. There are many cryptographic algorithms are developed by many researchers to achieve the information security but it is essential to plan an algorithms in such a manner that an opponent cannot defeat its purpose. These algorithms basically contains of some arithmetic and logical operations which are complicated and time consuming. In addition if the related system is of high speed, the speed of the fundamental cryptographic algorithms additionally should be considered. Cryptographic algorithms utilize modular multiplication intensively. Most basic algorithms are the RSA Algorithm, named after its creators Rivest, Shamir and Adleman, and the recently rising elliptic curved cryptosystems (ECC) descibed. While performance and Area stay to be the two noteworthy outline tolls, control consumption has turned into a basic worry in the present VLSI framework design. There are numerous executions of high– radix regular multipliers exist however, there are few high– radix secluded multipliers in the writing are talked about. In this work a broad overview of writing review in light of Montgomery Multiplication has given.